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cy8c24894 automotive psoc ? programmable system-on-chip? cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-53754 rev. *d revised june 2, 2011 features automotive electronics council (aec) qualified powerful harvard-architecture processor ? m8c processor speeds up to 24 mhz ? two 8 8 multiply, 32-bit accumulate ? low power at high speed ? operating voltage: 3.0 v to 5.25 v ? automotive temperature range: ?40 c to +85 c advanced peripherals (psoc ? blocks) ? six rail-to-rail analog psoc blocks provide: ? up to 14-bit analog-to-digital converters (adcs) ? up to 9-bit digital-to-analog converters (dacs) ? programmable gain amplifiers (pgas) ? programmable filters and comparators ? four digital psoc blocks provide: ? 8- to 32-bit timers, counters, and pulse-width modulators (pwms) ? cyclic redundancy check (crc) and pseudo-random sequence (prs) modules ? full- or half-duplex uart ? spi master or slave ? connectable to all general purpose i/o (gpio) pins ? complex peripherals by combining blocks ? capacitive sensing application capability flexible on-chip memory ? 16 kb flash program storage, 1000 erase/write cycles ? 1 kb sram data storage ? in-system serial programming (issp) ? partial flash updates ? flexible protection modes ? eeprom emulation in flash programmable pin configurations ? 25 ma sink, 10 ma drive on all gpios ? pull-up, pull-down, high z, strong, or open-drain drive modes on all gpios ? up to 47 analog inputs on gpios ? two 30 ma analog outputs on gpios ? configurable interrupt on all gpios precision, programmable clocking ? internal 4% 24/48 mhz oscillator ? internal low-speed, low-power oscillator for watchdog and sleep functionality ? optional external oscillator, up to 24 mhz additional system resources ? i 2 c? slave, master, or multimas ter operation up to 400 khz ? watchdog and sleep timers ? user-configurable lvd ? integrated supervisory circuit ? on-chip precision voltage reference complete development tools ? free development software (psoc designer?) ? full-featured in-circuit em ulator (ice) and programmer ? full-speed emulation ? complex breakpoint structure ? 128 kb trace memory logic block diagram input analog muxing digital system sram 1k interrupt controller sleep and watchdog clock sources (includes imo and ilo) global digital interconnect global analog interconnect psoc core cpu core (m8c) srom flash 16k digital block array digital clocks system resources analog system analog ref. port 5 port 4 port 3 port 2 port 1 port 0 analog drivers analog block array internal voltage ref . por and lvd system resets 2 macs decimator type 2 i2c port 7 s y s t e m b u s [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 2 of 46 contents psoc functional overview .............................................. 3 the psoc core ........................................................... 3 the digital system ...................................................... 3 the analog system ..................................................... 4 additional system resources ..................................... 5 psoc device characteristics . ..................................... 5 getting started .................................................................. 6 application notes ........................................................ 6 development kits ........................................................ 6 training ....................................................................... 6 cypros consultants .................................................... 6 solutions library .......................................................... 6 technical support ....................................................... 6 development tools .......................................................... 6 psoc designer software subsyst ems .......... .............. 6 designing with psoc designer ....................................... 7 select user modules ................................................... 7 configure user modules .............................................. 7 organize and connect .............. .............. ........... ......... 7 generate, verify, and debug ....................................... 7 pinouts .............................................................................. 8 56-pin part pinout (with xres pin) ............................ 8 registers ........................................................................... 9 register conventions .................................................. 9 register mapping tables ............................................ 9 register map bank 0 table: user space ................. 10 register map bank 1 table: configuration space ... 11 electrical specifications ................................................ 12 absolute maximum ratings ... .................................... 13 operating temperature ............................................. 13 dc electrical characteristics ..................................... 14 ac electrical characteristics ..................................... 26 packaging information ................................................... 34 thermal impedances ................................................. 34 solder reflow specifications ..................................... 34 tape and reel information .... .............. .............. ........ 35 development tool selection .. .............. .............. ........... 36 software .................................................................... 36 development kits ...................................................... 36 evaluation tools ........................................................ 36 device programmers ............. .................................... 37 accessories (emulation and programming) .............. 37 ordering information ...................................................... 38 ordering code definitions ..... .................................... 38 reference information ................................................... 39 acronyms .................................................................. 39 reference documents ............................................... 39 document conventions ......... .................................... 40 glossary .................................................................... 40 document history page ................................................. 45 sales, solutions, and legal information ...................... 46 worldwide sales and design s upport ......... .............. 46 products .................................................................... 46 psoc solutions ......................................................... 46 [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 3 of 46 psoc functional overview the psoc family consists of many programmable system-on-chip with on-chip controller devices. all psoc family devices are designed to replace traditional microcontroller units (mcus), system ics, and the numerous discrete components that surround them. configurable analog, digital, and inter- connect circuitry enable a high leve l of integration in a host of industrial, consumer, and communication applications. this architecture allows the user to create customized peripheral configurations that match the requirements of each individual application. additionally, a fast cpu, flash program memory, sram data memory, and configurable i/o are included in a range of convenient pinouts and packages. the psoc architecture, as illustrated in the logic block diagram on page 1 , is comprised of four main areas: psoc core, digital system, analog system, and system resources. configurable global busing allows all the device resources to be combined into a complete custom system. the psoc cy8c24x94 devices can have up to seven i/o ports that connect to the global digital and analog interconnects, providing access to four digital blocks and six analog blocks. the psoc core the psoc core is a powerful engine that supports a rich feature set. the core includes a cpu, me mory, clocks, and configurable gpios. the m8c cpu core is a powerful processor with speeds up to 24 mhz, providing a four-mips 8-bit harvard architecture micro- processor. the cpu uses an interrupt controller with up to 20 vectors, to simplify programmi ng of real-time embedded events. program execution is timed and protected using the included sleep timer and watchdog timer (wdt). memory encompasses 16 kb of flash for program storage, 1 kb of sram for data storage, and up to 2 kb of emulated eeprom using the flash. program flash has four protection levels on blocks of 64 bytes, a llowing customized software ip protection. the psoc device incorporates flex ible internal clock generators, including a 24-mhz internal main oscillator (imo) accurate to 4% over temperature and volta ge. the 24-mhz imo can also be doubled to 48 mhz for use by the digital system. a low power 32-khz internal low-speed osc illator (ilo) is provided for the sleep timer and wdt. the clo cks, together with programmable clock dividers (as system resources), provide the flexibility to integrate almost any timing requ irement into the psoc device. psoc gpios provide connection to the cpu, digital resources, and analog resources of the device. each pin?s drive mode may be selected from eight options, allowing great flexibility in external interfacing. every pin is also capable of generating a system interrupt. the digital system the digital system is composed of four digital psoc blocks. each block is an 8-bit resource used alone or combined with other blocks to form 8-, 16-, 24-, and 32-bit peripherals, which are called user modules. figure 1. digital system block diagram digital peripheral configurations include those listed below. pwms (8- to 32-bit) pwms with dead band (8- to 24-bit) counters (8- to 32-bit) timers (8- to 32-bit) full- or half-duplex 8-bit uart with selectable parity spi master and slave i 2 c master, slave, or multimaster (implemented in a dedicated i 2 c block) cyclic redundancy checker/generator (16-bit) infrared data association (irda) prs generators (8- to 32-bit) the digital blocks can be conne cted to any gpio through a series of global buses that can route any signal to any pin. the buses also allow signal multiplexing and performing logic opera- tions. this configurability frees yo ur designs from the constraints of a fixed peripheral controller. digital blocks are provided in rows of four, where the number of blocks varies by psoc device family. this allows you the optimum choice of system resource s for your application. family resources are shown in table 1 on page 5 . digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital psoc block array to analog system 8 row input configuration row output configuration 8 8 8 row 0 dbb00 dbb01 dcb02 dcb03 4 4 gie[7:0] gio[7:0] goe[7:0] goo[7:0] global digital interconnect port 1 port 0 port 3 port 2 port 5 port 4 port 7 [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 4 of 46 the analog system the analog system is composed of six configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. analog peripherals are very flexible and can be customized to support specific application requirements. some of the more common psoc analog functions (most available as user modules) are listed below. adcs (up to two, with 6- to 14-bit resolution, selectable as incremental, delta-sigma, or successive approximation register (sar)) filters (two- and four-pole band pass, low pass, and notch) amplifiers (up to two, with selectable gain to 48x) instrumentation amplifiers (one with selectable gain to 93x) comparators (up to two, with 16 selectable thresholds) dacs (up to two, with 6- to 9-bit resolution) multiplying dacs (up to two, with 6- to 9-bit resolution) high current output drivers (two with 30 ma drive) 1.3-v reference (as a system resource) dtmf dialer modulators correlators peak detectors many other topologies possible analog blocks are arranged in a co lumn of three, which includes one continuous time (ct) and two switched capacitor (sc) blocks, as shown in figure 2 . figure 2. analog system block diagram the analog multiplexer system the analog mux bus can connect to every gpio pin in ports 0-5. pins are connected to the bus individually or in any combination. the bus also connects to the analog system for analysis with comparators and adcs. it can be split into two sections for simul- taneous dual-channel processing. an additional 8:1 analog input multiplexer provides a second path to bring port 0 pins to the analog array. switch control logic enables sele cted pins to precharge continu- ously under hardware control. this enables capacitive measurement for applications such as touch sensing. other multiplexer applications include: track pad, finger sensing. chip-wide mux that allows analog input from up to 47 i/o pins. crosspoint connection between any i/o pin combination. acb00 acb01 block array array input c on fig uratio n aci1[1:0] asd20 aci0[1:0] p0[6] p0[4] p0[2] p0[0] p2[2] p2[0] p2[6] p2[4] refin agndin p0[7] p0[5] p0[3] p0[1] p2[3] p2[1] reference generators agndin r efin bandgap refhi reflo agnd asd11 asc21 asc10 interface to digital system m8c interface (address bus, data bus, etc.) analog reference a ll io (except port 7) analog mux bus [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 5 of 46 additional system resources system resources provide additional capability useful for complete systems. additional resources include a multiplier, decimator, lvd, and power-on re set (por). brief statements describing the merits of each resource follow. digital clock dividers provide three customizable clock frequencies for use in applications. the clocks can be routed to both the digital and analog systems. additional clocks are generated using digital psoc blocks as clock dividers. two multiply accumulates (macs) provide fast 8-bit multipliers with 32-bit accumulate, to assist in both general math and digital filters. the decimator provides a custom hardware filter for digital signal processing applications including creation of delta- sigma adcs. the i 2 c module provides 0 to 400 kh z communication over two wires. slave, master, and mu lti-master modes are all supported. lvd interrupts can signal the application of falling voltage levels, while the advanced por circuit eliminates the need for a system supervisor. an internal 1.3-v voltage reference provides an absolute reference for the analog system, including adcs and dacs. versatile analog mu ltiplexer system. psoc device characteristics depending on your psoc device characteri stics, the digital and analog systems can have varying numbers of digital and analog blocks. the following table lists the resources available for spec ific psoc device groups. the device covered by this datasheet is shown in the highlighted row of the table. table 1. psoc device characteristics psoc part number digital i/o digital rows digital blocks analog inputs analog outputs analog columns analog blocks sram size flash size cy8c29x66 [1] up to 64 4 16 up to 12 4 4 12 2 k 32 k cy8c28xxx up to 44 up to 3 up to 12 up to 44 up to 4 up to 6 up to 12 + 4 [2] 1 k 16 k cy8c27x43 up to 44 2 8 up to 12 4 4 12 256 16 k cy8c24x94 [1] up to 56 1 4 up to 48 2 2 6 1 k 16 k cy8c24x23a [1] up to 24 1 4 up to 12 2 2 6 256 4 k cy8c23x33 up to 26 1 4 up to 12 2 2 4 256 8 k cy8c22x45 [1] up to 38 2 8 up to 38 0 4 6 [2] 1 k 16 k cy8c21x45 [1] up to 24 1 4 up to 24 0 4 6 [2] 512 8 k cy8c21x34 [1] up to 28 1 4 up to 28 0 2 4 [2] 512 8 k cy8c21x23 up to 16 1 4 up to 8 0 2 4 [2] 256 4 k cy8c20x34 [1] up to 28 0 0 up to 28 0 0 3 [2,3] 512 8 k cy8c20xx6 up to 36 0 0 up to 36 0 0 3 [2,3] up to 2 k up to 32 k notes 1. automotive qualified devices available in this group. 2. limited analog functionality. 3. two analog blocks and one capsense ? block. [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 6 of 46 getting started for in depth information, along with detailed programming details, see the psoc ? technical reference manual . for up-to-date ordering, packaging, and electrical specification information, see the latest psoc device datasheets on the web. application notes cypress application notes are an excellent introduction to the wide variety of possi ble psoc designs. development kits psoc development kits are available online from and through a growing number of regional and global distributors, which include arrow, avnet, digi-key, farnell, future electronics, and newark. training free psoc technical training (on demand, webinars, and workshops), which is available online via www.cypress.com , covers a wide variety of topics and skill levels to assist you in your designs. cypros consultants certified psoc consultants offer everything from technical assis- tance to completed psoc designs. to contact or become a psoc consultant go to the cypros consultants web site. solutions library visit our growing library of solution focused designs . here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. technical support technical support ? including a searchable knowledge base articles and technical forums ? is also available online. if you cannot find an answer to your question, call our technical support hotline at 1-800-541-4736. development tools psoc designer? is the revolutionary integrated design environment (ide) that you can us e to customize psoc to meet your specific application require ments. psoc designer software accelerates system design and ti me to market. develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. then, customize your design by leveraging the dynamically generated application programming interface (api) libraries of code. finally, debug and test your designs with the integrated debug environment, incl uding in-circuit emulation and standard software debug features. psoc designer includes: application editor graphical user interface (gui) for device and user module configuration and dynamic reconfiguration extensive user module catalog integrated source-code editor (c and assembly) free c compiler with no size restrictions or time limits built-in debugger in-circuit emulation built-in support for communication interfaces: ? hardware and software i 2 c slaves and masters ? full-speed usb 2.0 ? up to four full-duplex universa l asynchronous receiver/trans- mitters (uarts), spi master and slave, and wireless psoc designer supports the entire library of psoc 1 devices and runs on windows xp, windows vista, and windows 7. psoc designer software subsystems design entry in the chip-level view, choose a ba se device to work with. then select different onboard analog and digital components that use the psoc blocks, which are called user modules. examples of user modules are analog-to-digital converters (adcs), digital-to-analog converters (d acs), amplifiers, and filters. configure the user modules for your chosen application and connect them to each other and to the proper pins. then generate your project. this prepopulates your project with apis and libraries that you can us e to program your application. the tool also supports easy development of multiple configura- tions and dynamic reconfiguration. dynamic reconfiguration makes it possible to change configurations at run time. in essence, this allows you to use more than 100 percent of psoc's resources for a given application. code generation tools the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. you can develop your design in c, assembly, or a combination of the two. assemblers . the assemblers allow you to merge assembly code seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. c language compilers . c language compilers are available that support the psoc family of devices. the products allow you to create complete c programs for the psoc family devices. the optimizing c compilers provide all of the features of c, tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger psoc designer has a debug environment that provides hardware in-circuit emulation, al lowing you to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow you to read and program and read and write data memory, and read and write i/o registers. you can read and write cpu registers, set and clear breakpoints, and provide program run, halt, and step control. the debugger also allows you to create a trac e buffer of registers and memory locations of interest. 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cy8c24894 document number: 001-53754 rev. *d page 7 of 46 online help system the online help system displays onl ine, context-sensitive help. designed for procedural and quick reference, each functional subsystem has its own context-se nsitive help. this system also provides tutorials and links to faqs and an online support forum to aid the designer. in-circuit emulator a low-cost, high-functionality in -circuit emulator (ice) is available for development support. this hardware can program single devices. the emulator consists of a base unit that connects to the pc using a usb port. the base unit is universal and operates with all psoc devices. emulation pods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full-speed (24-mhz) operation. designing with psoc designer the development process for the psoc ? device differs from that of a traditional fixed function mi croprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and by lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variet y of user-selectable functions. the psoc development process is summarized in four steps: 1. select user modules . 2. configure user modules. 3. organize and connect. 4. generate, verify, and debug. select user modules psoc designer provides a library of prebuilt, pretested hardware peripheral components called ?user modules.? user modules make selecting and implementing peripheral devices, both analog and digital, simple. configure user modules each user module that you select establishes the basic register settings that implement the select ed function. they also provide parameters and properties that allow you to tailor their precise configuration to your particular application. for example, a pulse width modulator (pwm) user module configures one or more digital psoc blocks, one for each 8 bits of resolution. the user module parameters permit you to establish the pulse width and duty cycle. configure the parame ters and properties to corre- spond to your chosen application. enter values directly or by selecting values from drop-down menus. all the user modules are documented in datasheets that may be viewed directly in psoc designer or on the cypress website. these user module datasheets explain the internal operat ion of the user module and provide performance specificatio ns. each datasheet describes the use of each user module parameter, and other information you may need to successfully implement your design. organize and connect you build signal chains at the chip level by interconnecting user modules to each other and the i/o pins. you perform the selection, configuration, and routing so that you have complete control over all on-chip resources. generate, verify, and debug when you are ready to test the hardware configuration or move on to developing code for the project, you perform the ?generate configuration files? step. this causes psoc designer to generate source code that automatic ally configures the device to your specification and provides the software for the system. the generated code provides application programming interfaces (apis) with high-level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. a complete code development environment allows you to develop and customize your applications in either c, assembly language, or both. the last step in the development process takes place inside psoc designer?s debugger (access by clicking the connect icon). psoc designer downloads the hex image to the ice where it runs at full speed. psoc designer debugging capabil- ities rival those of systems cost ing many times more. in addition to traditional single-step, run-to-breakpoint and watch-variable features, the debug interface prov ides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 8 of 46 pinouts the automotive cy8c24x94 psoc devic e is available in a variety of packages which are listed and illustrated in the following ta bles. every port pin (labeled with a ?p?) is capable of digital i/o. however, v ss , v dd , and xres are not capable of digital i/o. 56-pin part pinout (with xres pin) table 2. 56-pin part pinout (qfn) pin no. type name description figure 3. cy8c24894 56-pin psoc device digital analog 1 i/o i, m p2[3] direct switched capacitor block input 2 i/o i, m p2[1] direct switched capacitor block input 3 i/o m p4[7] 4 i/o m p4[5] 5 i/o m p4[3] 6 i/o m p4[1] 7 i/o m p3[7] 8 i/o m p3[5] 9 i/o m p3[3] 10 i/o m p3[1] 11 i/o m p5[7] 12 i/o m p5[5] 13 i/o m p5[3] 14 i/o m p5[1] 15 i/o m p1[7] i 2 c serial clock (scl) 16 i/o m p1[5] i 2 c serial data (sda) 17 i/o m p1[3] 18 i/o m p1[1] i 2 c scl, issp sclk [4] 19 power v ss ground connection 20 dnc do not connect anything to this pin 21 dnc do not connect anything to this pin 22 power v dd supply voltage 23 i/o p7[7] 24 i/o p7[0] 25 i/o m p1[0] i 2 c sda, issp sdata [4] 26 i/o m p1[2] 27 i/o m p1[4] optional external clock (extclk) input 28 i/o m p1[6] 29 i/o m p5[0] 30 i/o m p5[2] pin no. type name description 31 i/o m p5[4] digital analog 32 i/o m p5[6] 45 i/o i, m p0[0] analog column mux input 33 i/o m p3[0] 46 i/o i, m p0[2] analog column mux input 34 i/o m p3[2] 47 i/o i, m p0[4] analog column mux input 35 i/o m p3[4] 48 i/o i, m p0[6] analog column mux input 36 input xres active high external reset with internal pull-down 49 power v dd supply voltage 37 i/o m p4[0] 50 power v ss ground connection 38 i/o m p4[2] 51 i/o i, m p0[7] analog column mux input 39 i/o m p4[4] 52 i/o i/o, m p0[5] analog column mux input and column output 40 i/o m p4[6] 53 i/o i/o, m p0[3] analog column mux input and column output 41 i/o i, m p2[0] direct switched capacitor block input 54 i/o i, m p0[1] analog column mux input 42 i/o i, m p2[2] direct switched capacitor block input 55 i/o m p2[7] 43 i/o m p2[4] external analog ground (agnd) input 56 i/o mp2[5] 44 i/o m p2[6] external voltage reference (vref) input ep power v ss exposed pad is not connec ted internally. connect to circuit ground for best performance legend a = analog, i = input, o = output, and m = analog mux input. note 4. these are the issp pins, which are not high z when coming out of reset state. see the psoc technical reference manual for details. ai, m, p2[3] ai, m, p2[1] m, p4[7] m, p4[5] m, p4[3] m, p4[1] m, p3[7] m, p3[5] m, p3[3] m, p3[1] m, p5[7] m, p5[5] m, p5[3] m, p5[1] i2c scl, m, p1[7] i2c sda, m, p1[5] m, p1[3] i2c scl, m, p1[1] v ss dnc v dd p7[7] p7[0] i2c sda, m, p1[0] m, p1[2] extclk, m, p1[4] m, p1[6] p2[4], m, ext. agnd p2[6], m, ext. vref p0[0], m, ai p0[2], m, ai p0[4], m, ai p0[6], m, ai v dd v ss p0[7], m, ai p0[5], m, aio p0[3], m, aio p0[1], m, ai p2[7], m p2[5], m 56 p2[2], ai, m p2[0], ai, m p4[6], m p4[4], m p4[2], m p4[0], m xres p3[4], m p3[2], m p3[0], m p5[6], m p5[4], m p5[2], m p5[0], m 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 dnc qfn (top view) [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 9 of 46 registers this section lists the registers of the automotive cy8c24x94 psoc device family. for detailed register information, refer to th e psoc technical reference manual . register conventions the register conventions specific to this section are listed in the following table. register mapping tables the psoc device has a total register address space of 512 bytes. the register space is re ferred to as i/o space and is divided into two banks. the xio bit in the flag register (cpu_f) determines which bank the user is currently in. when the xio bit is set the user is in bank 1. note in the following register mapping tables, blank fields are reserved and should not be accessed. convention description r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 10 of 46 register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw 40 asc10cr0 80 rw c0 prt0ie 01 rw 41 asc10cr1 81 rw c1 prt0gs 02 rw 42 asc10cr2 82 rw c2 prt0dm2 03 rw 43 asc10cr3 83 rw c3 prt1dr 04 rw 44 asd11cr0 84 rw c4 prt1ie 05 rw 45 asd11cr1 85 rw c5 prt1gs 06 rw 46 asd11cr2 86 rw c6 prt1dm2 07 rw 47 asd11cr3 87 rw c7 prt2dr 08 rw 48 88 c8 prt2ie 09 rw 49 89 c9 prt2gs 0a rw 4a 8a ca prt2dm2 0b rw 4b 8b cb prt3dr 0c rw 4c 8c cc prt3ie 0d rw 4d 8d cd prt3gs 0e rw 4e 8e ce prt3dm2 0f rw 4f 8f cf prt4dr 10 rw 50 asd20cr0 90 rw cur_pp d0 rw prt4ie 11 rw 51 asd20cr1 91 rw stk_pp d1 rw prt4gs 12 rw 52 asd20cr2 92 rw d2 prt4dm2 13 rw 53 asd20cr3 93 rw idx_pp d3 rw prt5dr 14 rw 54 asc21cr0 94 rw mvr_pp d4 rw prt5ie 15 rw 55 asc21cr1 95 rw mvw_pp d5 rw prt5gs 16 rw 56 asc21cr2 96 rw i2c_cfg d6 rw prt5dm2 17 rw 57 asc21cr3 97 rw i2c_scr d7 # 18 58 98 i2c_dr d8 rw 19 59 99 i2c_mscr d9 # 1a 5a 9a int_clr0 da rw 1b 5b 9b int_clr1 db rw prt7dr 1c rw 5c 9c int_clr2 dc rw prt7ie 1d rw 5d 9d int_clr3 dd rw prt7gs 1e rw 5e 9e int_msk3 de rw prt7dm2 1f rw 5f 9f int_msk2 df rw dbb00dr0 20 # amx_in 60 rw a0 int_msk0 e0 rw dbb00dr1 21 w amuxcfg 61 rw a1 int_msk1 e1 rw dbb00dr2 22 rw 62 a2 int_vc e2 rc dbb00cr0 23 # arf_cr 63 rw a3 res_wdt e3 w dbb01dr0 24 # cmp_cr0 64 # a4 dec_dh e4 rc dbb01dr1 25 w asy_cr 65 # a5 dec_dl e5 rc dbb01dr2 26 rw cmp_cr1 66 rw a6 dec_cr0 e6 rw dbb01cr0 27 # 67 a7 dec_cr1 e7 rw dcb02dr0 28 # 68 mul1_x a8 w mul0_x e8 w dcb02dr1 29 w 69 mul1_y a9 w mul0_y e9 w dcb02dr2 2a rw 6a mul1_dh aa r mul0_dh ea r dcb02cr0 2b # 6b mul1_dl ab r mul0_dl eb r dcb03dr0 2c # tmp_dr0 6c rw acc1_dr1 ac rw acc0_dr1 ec rw dcb03dr1 2d w tmp_dr1 6d rw acc1_dr0 ad rw acc0_dr0 ed rw dcb03dr2 2e rw tmp_dr2 6e rw acc1_dr3 ae rw acc0_dr3 ee rw dcb03cr0 2f # tmp_dr3 6f rw acc1_dr2 af rw acc0_dr2 ef rw 30 acb00cr3 70 rw rdi0ri b0 rw f0 31 acb00cr0 71 rw rdi0syn b1 rw f1 32 acb00cr1 72 rw rdi0is b2 rw f2 33 acb00cr2 73 rw rdi0lt0 b3 rw f3 34 acb01cr3 74 rw rdi0lt1 b4 rw f4 35 acb01cr0 75 rw rdi0ro0 b5 rw f5 36 acb01cr1 76 rw rdi0ro1 b6 rw f6 37 acb01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd dac_d fd rw 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 11 of 46 register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw 40 asc10cr0 80 rw c0 prt0dm1 01 rw 41 asc10cr1 81 rw c1 prt0ic0 02 rw 42 asc10cr2 82 rw c2 prt0ic1 03 rw 43 asc10cr3 83 rw c3 prt1dm0 04 rw 44 asd11cr0 84 rw c4 prt1dm1 05 rw 45 asd11cr1 85 rw c5 prt1ic0 06 rw 46 asd11cr2 86 rw c6 prt1ic1 07 rw 47 asd11cr3 87 rw c7 prt2dm0 08 rw 48 88 c8 prt2dm1 09 rw 49 89 c9 prt2ic0 0a rw 4a 8a ca prt2ic1 0b rw 4b 8b cb prt3dm0 0c rw 4c 8c cc prt3dm1 0d rw 4d 8d cd prt3ic0 0e rw 4e 8e ce prt3ic1 0f rw 4f 8f cf prt4dm0 10 rw 50 90 gdi_o_in d0 rw prt4dm1 11 rw 51 asd20cr1 91 rw gdi_e_in d1 rw prt4ic0 12 rw 52 asd20cr2 92 rw gdi_o_ou d2 rw prt4ic1 13 rw 53 asd20cr3 93 rw gdi_e_ou d3 rw prt5dm0 14 rw 54 asc21cr0 94 rw d4 prt5dm1 15 rw 55 asc21cr1 95 rw d5 prt5ic0 16 rw 56 asc21cr2 96 rw d6 prt5ic1 17 rw 57 asc21cr3 97 rw d7 18 58 98 mux_cr0 d8 rw 19 59 99 mux_cr1 d9 rw 1a 5a 9a mux_cr2 da rw 1b 5b 9b mux_cr3 db rw prt7dm0 1c rw 5c 9c dc prt7dm1 1d rw 5d 9d osc_go_en dd rw prt7ic0 1e rw 5e 9e osc_cr4 de rw prt7ic1 1f rw 5f 9f osc_cr3 df rw dbb00fn 20 rw clk_cr0 60 rw a0 osc_cr0 e0 rw dbb00in 21 rw clk_cr1 61 rw a1 osc_cr1 e1 rw dbb00ou 22 rw abf_cr0 62 rw a2 osc_cr2 e2 rw 23 amd_cr0 63 rw a3 vlt_cr e3 rw dbb01fn 24 rw cmp_go_en 64 rw a4 vlt_cmp e4 r dbb01in 25 rw 65 a5 e5 dbb01ou 26 rw amd_cr1 66 rw a6 e6 27 alt_cr0 67 rw a7 e7 dcb02fn 28 rw 68 a8 imo_tr e8 w dcb02in 29 rw 69 a9 ilo_tr e9 w dcb02ou 2a rw 6a aa bdg_tr ea rw 2b 6b ab eco_tr eb w dcb03fn 2c rw tmp_dr0 6c rw ac mux_cr4 ec rw dcb03in 2d rw tmp_dr1 6d rw ad mux_cr5 ed rw dcb03ou 2e rw tmp_dr2 6e rw ae ee 2f tmp_dr3 6f rw af ef 30 acb00cr3 70 rw rdi0ri b0 rw f0 31 acb00cr0 71 rw rdi0syn b1 rw f1 32 acb00cr1 72 rw rdi0is b2 rw f2 33 acb00cr2 73 rw rdi0lt0 b3 rw f3 34 acb01cr3 74 rw rdi0lt1 b4 rw f4 35 acb01cr0 75 rw rdi0ro0 b5 rw f5 36 acb01cr1 76 rw rdi0ro1 b6 rw f6 37 acb01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd dac_cr fd rw 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 12 of 46 electrical specifications this section presents the dc and ac electric al specifications of the automotive cy8c24 x94 psoc device family. for the most up t o date electrical specifications, confirm that you have the most recent datasheet by visiting http://www.cypress.com . specifications are valid for ?40 c t a 85 c and t j 100 c, except where noted. figure 4. voltage versus cpu frequency 5.25 4.75 93 khz 24 mhz cpu frequency (nominal setting) v dd voltage (v) 0 12 mhz 3.0 v a li d o p e r a t i n g r e g i o n [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 13 of 46 absolute maximum ratings exceeding maximum ratings may shorten the useful li fe of the device. user guidelines are not tested. operating temperature table 3. absolute maximum ratings symbol description min typ max units notes t stg storage temperature ?55 25 +100 c higher storage temperatures reduce data retention time. recommended storage temperature is +25 c 25 c. time spent in storage at a temperature greater than 65 c counts toward the flash dr electrical specification in table 16 on page 25 . t baketemp bake temperature ? 125 see package label c t baketime bake time see package label ? 72 hours t a ambient temperature with power applied ?40 ? +85 c v dd supply voltage on v dd relative to v ss ?0.5 ? +6.0 v v io dc input voltage v ss ? 0.5 ? v dd + 0.5 v v io2 dc voltage applied to tri-state v ss ? 0.5 ? v dd + 0.5 v i mio maximum current into any port pin ?25 ? +50 ma i maio maximum current into any port pin configured as analog driver ?50 ? +50 ma esd electro static discharge voltage 2000 ? ? v human body model esd. lu latch-up current ? ? 200 ma table 4. operating temperature symbol description min typ max units notes t a ambient temperature ?40 ? +85 c t j junction temperature ?40 ? +100 c the temperature rise from ambient to junction is package specific. see table 28 on page 34 . the user must limit the power consumption to comply with this requirement. [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 14 of 46 dc electrical characteristics dc chip level specifications ta b l e 5 lists guaranteed maximum and minimum specifications for th e voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. dc gpio specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 5. dc chip-level specifications symbol description min typ max units notes v dd supply voltage 3.0 ? 5.25 v see dc por and lvd specifications, table 15 on page 24 . i dd5 supply current, imo = 24 mhz, v dd = 5 v ? 14 27 ma conditions are v dd = 5.0 v, t a = 25 c, cpu = 3 mhz, 48 mhz disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 93.75 khz, analog power = off. i dd3 supply current, imo = 24 mhz, v dd = 3.3 v ? 8 14 ma conditions are v dd = 3.3 v, t a = 25 c, cpu = 3 mhz, 48 mhz disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 0.367 khz, analog power = off. i sb sleep (mode) current with por, lvd, sleep timer, and wdt. [5] ? 3 6.5 a conditions are with ilo active, v dd = 3.3 v, ?40 c t a 55 c, analog power = off. i sbh sleep (mode) current with por, lvd, sleep timer, and wdt at high temperature. [5] ? 4 25 a conditions are with ilo active, v dd = 3.3 v, 55 c < t a 85 c, analog power = off. table 6. dc gpio specifications symbol description min typ max units notes r pu pull-up resistor 4 5.6 8 k r pd pull-down resistor 4 5.6 8 k also applies to the internal pull-down resistor on the xres pin v oh high output level v dd ? 1.0 ? ? v i oh = 10 ma, v dd = 4.75 v to 5.25 v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). 80 ma maximum combined i oh budget. v ol low output level ? ? 0.75 v i ol = 25 ma, v dd = 4.75 v to 5.25 v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). 200 ma maximum combined i ol budget. i oh high level source current 10 ? ? ma v oh v dd ? 1.0 v, see the limitations of the total current in the note for v oh . i ol low level sink current 25 ? ? ma v ol 0.75 v, see the limitations of the total current in the note for v ol . v il input low level ? ? 0.8 v v dd = 3.0 v to 5.25 v. v ih input high level 2.1 ? ? v v dd = 3.0 v to 5.25 v. v h input hysterisis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. t a = 25 c. c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. t a = 25 c. note 5. standby current includes all functions (por, lvd, wdt, sleep timer) needed for reliable system operation. this should be comp ared with devices that have similar functions enabled. [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 15 of 46 dc operational amplifier specifications ta b l e 7 and table 8 on page 16 list the guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. the operational amplifier is a component of both the analog cont inuous time (ct) psoc blocks and the analog switched capacitor (sc) psoc blocks. the guaranteed spec ifications are measured in the analog conti nuous time psoc block. table 7. 5-v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset volta ge (absolute value) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ?1.6 1.3 1.2 10 8 7.5 mv mv mv ? ? tcv osoa average input offset voltage drift ? 7.0 35.0 v/ c i eboa input leakage current (port 0 analog pins) ? 20 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. t a = 25 c. v cmoa common mode voltage range all cases, except highest power = high, opamp bias = high 0.0 0.5 ? ? v dd v dd ? 0.5 v v the common-mode input voltage range is measured through an analog output buffer. the specifi- cation includes the limitations imposed by the characteristics of the analog output buffer. g oloa open loop gain power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high 60 60 80 ? ? ? ? ? ? db db db specification is applicable at high power. for all other bias modes (except high power, high opamp bias), minimum is 60 db. v ohighoa high output voltage swing (internal signals) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high v dd ? 0.2 v dd ? 0.2 v dd ? 0.5 ? ? ? ? ? ? v v v v olowoa low output voltage swing (internal signals) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 0.2 0.2 0.5 v v v i soa supply current (including associated agnd buffer) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 400 500 800 1200 2400 4600 800 900 1000 1600 3200 6400 a a a a a a psrr oa supply voltage rejection ratio 65 80 ? db v ss v in (v dd ? 2.25 v) or (v dd ? 1.25 v) v in v dd . [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 16 of 46 dc low power comparator specifications ta b l e 9 lists guaranteed maximum and minimum specifications for th e voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v at 25 c and are for design guidance only. table 8. 3.3-v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ? ? ? 1.65 1.32 ? 10 8 ? mv mv mv power = high, opamp bias = high setting is not allowed for 3.3 v v dd operation tcv osoa average input offset vo ltage drift ? 7.0 35.0 v/c i eboa input leakage current (port 0 analog pins) ? 20 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. t a = 25 c. v cmoa common mode voltage range 0.2 ? v dd ? 0.2 v the common-mode input voltage range is measured through an analog output buffer. the specification includes the limitations imposed by the characteristics of the analog output buffer. g oloa open loop gain power = low, opamp bias = low power = medium, opamp bias = low power = high, opamp bias = low 60 60 80 ? ? ? ? ? ? db db db specification is applicable at low opamp bias. for high opamp bias mode (except high power, high opamp bias), minimum is 60 db. v ohighoa high output voltage swin g (internal signals) power = low, opamp bias = low power = medium, opamp bias = low power = high, opamp bias = low v dd ? 0.2 v dd ? 0.2 v dd ? 0.2 ? ? ? ? ? ? v v v v olowoa low output voltage swing (internal signals) power = low, opamp bias = low power = medium, opamp bias = low power = high, opamp bias = low ? ? ? ? ? ? 0.2 0.2 0.2 v v v i soa supply current (including associated agnd buffer) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 400 500 800 1200 2400 ? 800 900 1000 1600 3200 ? a a a a a a power = high, opamp bias = high setting is not allowed for 3.3 v v dd operation psrr oa supply voltage rejection ratio 65 80 ? db v ss v in (v dd ? 2.25) or (v dd ? 1.25 v) v in v dd table 9. dc low power comparator specifications symbol description min typ max units notes v reflpc low power comparator (lpc) reference voltage range 0.2 ? v dd ? 1.0 v i slpc lpc supply current ? 10 55 a v oslpc lpc voltage offset ? 2.5 55 mv [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 17 of 46 dc analog output bu ffer specifications ta b l e 1 0 and table 11 on page 18 list the guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 10. 5-v dc analog output buffer specifications symbol description min typ max units notes v osob input offset voltage (absolute value) ? 3 12 mv tcv osob average input offset voltage drift ? +6 ? v/c v cmob common mode input voltage range 0.5 ? v dd ? 1.0 v r outob output resistance power = low power = high ? ? 0.6 0.6 ? ? v ohighob high output voltage swing (load = 32 to v dd /2) power = low power = high 0.5 v dd + 1.1 0.5 v dd + 1.1 ? ? ? ? v v v olowob low output voltage swing (load = 32 to v dd /2) power = low power = high ? ? ? ? 0.5 v dd ? 1.3 0.5 v dd ? 1.3 v v i sob supply current including opamp bias cell (no load) power = low power = high ? ? 1.1 2.6 5.1 8.8 ma ma psrr ob supply voltage rejection ratio 53 64 ? db (0.5 v dd ? 1.3) v out (v dd ? 2.3). c l load capacitance ? ? 200 pf this specification applies to the external circuit that is being driven by the analog output buffer. [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 18 of 46 table 11. 3.3-v dc analog output buffer specifications symbol description min typ max units notes v osob input offset voltage (absolute value) ? 3 12 mv tcv osob average input offset voltage drift ? +6 ? v/c v cmob common mode input voltage range 0.5 ? v dd ? 1.0 v r outob output resistance power = low power = high ? ? 1 1 ? ? v ohighob high output voltage swing (load = 1 k to v dd /2) power = low power = high 0.5 v dd + 1.0 0.5 v dd + 1.0 ? ? ? ? v v v olowob low output voltage swing (load = 1 k to v dd /2) power = low power = high ? ? ? ? 0.5 v dd ? 1.0 0.5 v dd ? 1.0 v v i sob supply current including opamp bias cell (no load) power = low power = high ? ? 0.8 2.0 2.0 4.3 ma ma psrr ob supply voltage rejection ratio 34 64 ? db (0.5 v dd ? 1.0) v out (0.5 v dd + 0.9). c l load capacitance ? ? 200 pf this specification applies to the external circuit that is being driven by the analog output buffer. [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 19 of 46 dc analog reference specifications ta b l e 1 2 and table 13 on page 22 list the guaranteed maximum and minimum specif ications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c. these are for design guidance only. the guaranteed specificati ons are measured through the analog ct psoc blocks. the power levels for ag nd refer to the power of the analog ct psoc block. the power levels for refhi and reflo refer to the analog reference control register. the limits state d for agnd include the offset error of the agnd buffer local to t he analog ct psoc block. reference control power is high. note avoid using p2[4] for digital signaling when using an analog resource that depends on the analog reference. some coupling of the digital signal may appear on the agnd. table 12. 5-v dc analog reference specifications reference arf_cr [5:3] reference power settings symbol reference description min typ max units 0b000 refpower = high opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.229 v dd /2 + 1.290 v dd /2 + 1.346 v v agnd agnd v dd /2 v dd /2 ? 0.038 v dd /2 v dd /2 + 0.040 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.356 v dd /2 ? 1.295 v dd /2 ? 1.218 v refpower = high opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.220 v dd /2 + 1.292 v dd /2 + 1.348 v v agnd agnd v dd /2 v dd /2 ? 0.036 v dd /2 v dd /2 + 0.036 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.357 v dd /2 ? 1.297 v dd /2 ? 1.225 v refpower = medium opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.221 v dd /2 + 1.293 v dd /2 + 1.351 v v agnd agnd v dd /2 v dd /2 ? 0.036 v dd /2 v dd /2 + 0.036 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.357 v dd /2 ? 1.298 v dd /2 ? 1.228 v refpower = medium opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.219 v dd /2 + 1.293 v dd /2 + 1.353 v v agnd agnd v dd /2 v dd /2 ? 0.037 v dd /2 ? 0.001 v dd /2 + 0.036 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.359 v dd /2 ? 1.299 v dd /2 ? 1.229 v 0b001 refpower = high opamp bias = high v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.092 p2[4] + p2[6] ? 0.011 p2[4] + p2[6] + 0.064 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.031 p2[4] ? p2[6] + 0.007 p2[4] ? p2[6] + 0.056 v refpower = high opamp bias = low v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.078 p2[4] + p2[6] ? 0.008 p2[4] + p2[6] + 0.063 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.031 p2[4] ? p2[6] + 0.004 p2[4] ? p2[6] + 0.043 v refpower = medium opamp bias = high v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.073 p2[4] + p2[6] ? 0.006 p2[4] + p2[6] + 0.062 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.032 p2[4] ? p2[6] + 0.003 p2[4] ? p2[6] + 0.038 v refpower = medium opamp bias = low v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.073 p2[4] + p2[6] ? 0.006 p2[4] + p2[6] + 0.062 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.034 p2[4] ? p2[6] + 0.002 p2[4] ? p2[6] + 0.037 v [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 20 of 46 0b010 refpower = high opamp bias = high v refhi ref high v dd v dd ? 0.037 v dd ? 0.007 v dd v v agnd agnd v dd /2 v dd /2 ? 0.036 v dd /2 ? 0.001 v dd /2 + 0.036 v v reflo ref low v ss v ss v ss + 0.005 v ss + 0.029 v refpower = high opamp bias = low v refhi ref high v dd v dd ? 0.034 v dd ? 0.006 v dd v v agnd agnd v dd /2 v dd /2 ? 0.036 v dd /2 ? 0.001 v dd /2 + 0.035 v v reflo ref low v ss v ss v ss + 0.004 v ss + 0.024 v refpower = medium opamp bias = high v refhi ref high v dd v dd ? 0.032 v dd ? 0.005 v dd v v agnd agnd v dd /2 v dd /2 ? 0.036 v dd /2 ? 0.001 v dd /2 + 0.035 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.022 v refpower = medium opamp bias = low v refhi ref high v dd v dd ? 0.031 v dd ? 0.005 v dd v v agnd agnd v dd /2 v dd /2 ? 0.037 v dd /2 ? 0.001 v dd /2 + 0.035 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.020 v 0b011 refpower = high opamp bias = high v refhi ref high 3 bandgap 3.760 3.884 4.006 v v agnd agnd 2 bandgap 2.522 2.593 2.669 v v reflo ref low bandgap 1.252 1.299 1.342 v refpower = high opamp bias = low v refhi ref high 3 bandgap 3.766 3.887 4.010 v v agnd agnd 2 bandgap 2.523 2.594 2.670 v v reflo ref low bandgap 1.252 1.297 1.342 v refpower = medium opamp bias = high v refhi ref high 3 bandgap 3.769 3.888 4.013 v v agnd agnd 2 bandgap 2.523 2.594 2.671 v v reflo ref low bandgap 1.251 1.296 1.343 v refpower = medium opamp bias = low v refhi ref high 3 bandgap 3.769 3.889 4.015 v v agnd agnd 2 bandgap 2.523 2.595 2.671 v v reflo ref low bandgap 1.251 1.296 1.344 v 0b100 refpower = high opamp bias = high v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.483 ? p2[6] 2.582 ? p2[6] 2.674 ? p2[6] v v agnd agnd 2 bandgap 2.522 2.593 2.669 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.524 ? p2[6] 2.600 ? p2[6] 2.676 ? p2[6] v refpower = high opamp bias = low v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.490 ? p2[6] 2.586 ? p2[6] 2.679 ? p2[6] v v agnd agnd 2 bandgap 2.523 2.594 2.669 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.523 ? p2[6] 2.598 ? p2[6] 2.675 ? p2[6] v refpower = medium opamp bias = high v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.493 ? p2[6] 2.588 ? p2[6] 2.682 ? p2[6] v v agnd agnd 2 bandgap 2.523 2.594 2.670 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.523 ? p2[6] 2.597 ? p2[6] 2.675 ? p2[6] v refpower = medium opamp bias = low v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.494 ? p2[6] 2.589 ? p2[6] 2.685 ? p2[6] v v agnd agnd 2 bandgap 2.523 2.595 2.671 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.522 ? p2[6] 2.596 ? p2[6] 2.676 ? p2[6] v table 12. 5-v dc analog reference specifications (continued) reference arf_cr [5:3] reference power settings symbol reference description min typ max units [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 21 of 46 0b101 refpower = high opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.218 p2[4] + 1.291 p2[4] + 1.354 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.335 p2[4] ? 1.294 p2[4] ? 1.237 v refpower = high opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.221 p2[4] + 1.293 p2[4] + 1.358 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.337 p2[4] ? 1.297 p2[4] ? 1.243 v refpower = medium opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.222 p2[4] + 1.294 p2[4] + 1.360 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.338 p2[4] ? 1.298 p2[4] ? 1.245 v refpower = medium opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.221 p2[4] + 1.294 p2[4] + 1.362 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.340 p2[4] ? 1.298 p2[4] ? 1.245 v 0b110 refpower = high opamp bias = high v refhi ref high 2 bandgap 2.513 2.593 2.672 v v agnd agnd bandgap 1.264 1.302 1.340 v v reflo ref low v ss v ss v ss + 0.008 v ss + 0.038 v refpower = high opamp bias = low v refhi ref high 2 bandgap 2.514 2.593 2.674 v v agnd agnd bandgap 1.264 1.301 1.340 v v reflo ref low v ss v ss v ss + 0.005 v ss + 0.028 v refpower = medium opamp bias = high v refhi ref high 2 bandgap 2.514 2.593 2.676 v v agnd agnd bandgap 1.264 1.301 1.340 v v reflo ref low v ss v ss v ss + 0.004 v ss + 0.024 v refpower = medium opamp bias = low v refhi ref high 2 bandgap 2.514 2.593 2.677 v v agnd agnd bandgap 1.264 1.300 1.340 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.021 v 0b111 refpower = high opamp bias = high v refhi ref high 3.2 bandgap 4.028 4.144 4.242 v v agnd agnd 1.6 bandgap 2.028 2.076 2.125 v v reflo ref low v ss v ss v ss + 0.008 v ss + 0.034 v refpower = high opamp bias = low v refhi ref high 3.2 bandgap 4.032 4.142 4.245 v v agnd agnd 1.6 bandgap 2.029 2.076 2.126 v v reflo ref low v ss v ss v ss + 0.005 v ss + 0.025 v refpower = medium opamp bias = high v refhi ref high 3.2 bandgap 4.034 4.143 4.247 v v agnd agnd 1.6 bandgap 2.029 2.076 2.126 v v reflo ref low v ss v ss v ss + 0.004 v ss + 0.021 v refpower = medium opamp bias = low v refhi ref high 3.2 bandgap 4.036 4.144 4.249 v v agnd agnd 1.6 bandgap 2.029 2.076 2.126 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.019 v table 12. 5-v dc analog reference specifications (continued) reference arf_cr [5:3] reference power settings symbol reference description min typ max units [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 22 of 46 table 13. 3.3-v dc analog reference specifications reference arf_cr [5:3] reference power settings symbol reference description min typ max units 0b000 refpower = high opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.200 v dd /2 + 1.290 v dd /2 + 1.365 v v agnd agnd v dd /2 v dd /2 ? 0.030 v dd /2 v dd /2 + 0.034 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.346 v dd /2 ? 1.292 v dd /2 ? 1.208 v refpower = high opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.196 v dd /2 + 1.292 v dd /2 + 1.374 v v agnd agnd v dd /2 v dd /2 ? 0.029 v dd /2 v dd /2 + 0.031 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.349 v dd /2 ? 1.295 v dd /2 ? 1.227 v refpower = medium opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.204 v dd /2 + 1.293 v dd /2 + 1.369 v v agnd agnd v dd /2 v dd /2 ? 0.030 v dd /2 v dd /2 + 0.030 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.351 v dd /2 ? 1.297 v dd /2 ? 1.229 v refpower = medium opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.189 v dd /2 + 1.294 v dd /2 + 1.384 v v agnd agnd v dd /2 v dd /2 ? 0.032 v dd /2 v dd /2 + 0.029 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.353 v dd /2 ? 1.297 v dd /2 ? 1.230 v 0b001 refpower = high opamp bias = high v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.105 p2[4] + p2[6] ? 0.008 p2[4] + p2[6] + 0.095 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.035 p2[4] ? p2[6] + 0.006 p2[4] ? p2[6] + 0.053 v refpower = high opamp bias = low v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.094 p2[4] + p2[6] ? 0.005 p2[4] + p2[6] + 0.073 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.033 p2[4] ? p2[6] + 0.002 p2[4] ? p2[6] + 0.042 v refpower = medium opamp bias = high v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.094 p2[4] + p2[6] ? 0.003 p2[4] + p2[6] + 0.075 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.035 p2[4] ? p2[6] p2[4] ? p2[6] + 0.038 v refpower = medium opamp bias = low v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.095 p2[4] + p2[6] ? 0.003 p2[4] + p2[6] + 0.080 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.038 p2[4] ? p2[6] p2[4] ? p2[6] + 0.038 v 0b010 refpower = high opamp bias = high v refhi ref high v dd v dd ? 0.119 v dd ? 0.005 v dd v v agnd agnd v dd /2 v dd /2 ? 0.028 v dd /2 v dd /2 + 0.029 v v reflo ref low v ss v ss v ss + 0.004 v ss + 0.022 v refpower = high opamp bias = low v refhi ref high v dd v dd ? 0.131 v dd ? 0.004 v dd v v agnd agnd v dd /2 v dd /2 ? 0.028 v dd /2 v dd /2 + 0.028 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.021 v refpower = medium opamp bias = high v refhi ref high v dd v dd ? 0.111 v dd ? 0.003 v dd v v agnd agnd v dd /2 v dd /2 ? 0.029 v dd /2 v dd /2 + 0.028 v v reflo ref low v ss v ss v ss + 0.002 v ss + 0.017 v refpower = medium opamp bias = low v refhi ref high v dd v dd ? 0.128 v dd ? 0.003 v dd v v agnd agnd v dd /2 v dd /2 ? 0.029 v dd /2 v dd /2 + 0.029 v v reflo ref low v ss v ss v ss + 0.002 v ss + 0.019 v [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 23 of 46 0b011 all power settings. not allowed for 3.3 v. ?? ? ? ? ? ? 0b100 all power settings. not allowed for 3.3 v. ?? ? ? ? ? ? 0b101 refpower = high opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.214 p2[4] + 1.291 p2[4] + 1.359 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.335 p2[4] ? 1.292 p2[4] ? 1.200 v refpower = high opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.219 p2[4] + 1.293 p2[4] + 1.357 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.335 p2[4] ? 1.295 p2[4] ? 1.243 v refpower = medium opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.222 p2[4] + 1.294 p2[4] + 1.356 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.337 p2[4] ? 1.296 p2[4] ? 1.244 v refpower = medium opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.224 p2[4] + 1.295 p2[4] + 1.355 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.339 p2[4] ? 1.297 p2[4] ? 1.244 v 0b110 refpower = high opamp bias = high v refhi ref high 2 bandgap 2.510 2.595 2.655 v v agnd agnd bandgap 1.276 1.301 1.332 v v reflo ref low v ss v ss v ss + 0.006 v ss + 0.031 v refpower = high opamp bias = low v refhi ref high 2 bandgap 2.513 2.594 2.656 v v agnd agnd bandgap 1.275 1.301 1.331 v v reflo ref low v ss v ss v ss + 0.004 v ss + 0.021 v refpower = medium opamp bias = high v refhi ref high 2 bandgap 2.516 2.595 2.657 v v agnd agnd bandgap 1.275 1.301 1.331 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.017 v refpower = medium opamp bias = low v refhi ref high 2 bandgap 2.520 2.595 2.658 v v agnd agnd bandgap 1.275 1.300 1.331 v v reflo ref low v ss v ss v ss + 0.002 v ss + 0.015 v 0b111 all power settings. not allowed for 3.3 v. ?? ? ? ? ? ? table 13. 3.3-v dc analog reference specifications (continued) reference arf_cr [5:3] reference power settings symbol reference description min typ max units [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 24 of 46 dc analog psoc block specifications ta b l e 1 4 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. dc por and lvd specifications ta b l e 1 5 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c and are for design guidance only. note the bits porlev and vm in the table below refer to bits in the vlt_cr register. see the psoc technical reference manual for more information on the vlt_cr register. table 14. dc analog psoc block specifications symbol description min typ max units notes r ct resistor unit value (continuous time) ? 12.2 ? k c sc capacitor unit value (switched capacitor) ? 80 ? ff table 15. dc por and lvd specifications symbol description min typ max units notes v ppor0 v ppor1 v ppor2 v dd value for ppor trip (negative ramp) porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? ? ? 2.82 4.39 4.55 ? ? ? v v v v dd must be greater than or equal to 2.5 v during startup, reset from the xres pin, or reset from watchdog. v ph0 v ph1 v ph2 ppor hysteresis porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? ? ? 92 0 0 ? ? ? mv mv mv v lvd0 v lvd1 v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 v lvd7 v dd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 3.02 [6] 3.12 3.24 4.12 4.62 4.78 [7] 4.87 4.96 v v v v v v v v notes 6. always greater than 50 mv above ppor (porlev = 00) for falling supply. 7. always greater than 50 mv above ppor (porlev = 10) for falling supply. [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 25 of 46 dc programming specifications ta b l e 1 6 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 16. dc programming specifications symbol description min typ max units notes v ddp v dd for programming and erase 4.5 5.0 5.5 v this specification applies to the functional requirements of external programmer tools v ddlv low v dd for verify 3.0 3.1 3.2 v this specification applies to the functional requirements of external programmer tools v ddhv high v dd for verify 5.1 5.2 5.3 v this specification applies to the functional requirements of external programmer tools v ddiwrite supply voltage for flash write operation 3.0 ? 5.25 v this specification applies to this device when it is executing internal flash writes i ddp supply current during programming or verify ? 15 30 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.1 ? ? v i ilp input current when applying v ilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull-down resistor. i ihp input current when applying v ihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull-down resistor. v olv output low voltage during programming or verify ? ? 0.75 v v ohv output high voltage during programming or verify v dd ? 1.0 ? v dd v flash enpb flash endurance (per block) [8, 9] 1,000 ? ? ? erase/write cycles per block. flash ent flash endurance (total) [9, 10] 256,000 ? ? ? erase/write cycles. flash dr flash data retention [9] 10 ? ? years notes 8. the erase/write cycle limit per block (flash enpb ) is only guaranteed if the device operates within one volt age range. voltage ranges are 3.0 v to 3.6 v and 4.75 v to 5.25 v. 9. for the full temperature range, the user must employ a temper ature sensor user module (flashtemp) or other temperature sensor , and feed the result to the temperature argument before writing. refer to the flash apis application note an2015 for more information. 10. the maximum total number of allowed erase/write cycles is the minimum flash enpb value multiplied by the number of flash blocks in the device. [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 26 of 46 ac electrical characteristics ac chip-level specifications ta b l e 1 7 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. notes 11. accuracy derived from imo with appropriate trim for v dd range. 12. see the individual user module datasheets for in formation on maximum frequencies for user modules. 13. refer to cypress jitter specifications application note, understanding datasheet jitter specifications for cypress timing products ? an5054 for more information. table 17. ac chip-level specifications symbol description min typ max units notes f imo245v imo frequency for 24 mhz (5 v nominal) 23.04 [11] 24 24.96 [11] mhz trimmed for 5 v operation using factory trim values. f imo243v imo frequency for 24 mhz (3.3 v nominal) 22.08 [11] 24 25.92 [11] mhz trimmed for 3.3 v operation using factory trim values. f cpu1 cpu frequency (5 v nominal) 0.090 [11] 24 24.96 [11] mhz slimo mode = 0. f cpu2 cpu frequency (3.3 v nominal) 0.086 [11] 12 12.96 [11] mhz slimo mode = 0. f blk5 digital psoc block frequency (5 v nominal) 0 48 49.92 [11,12] mhz refer to the ac digital block specifications . f blk3 digital psoc block frequency (3.3 v nominal) 0 24 25.92 [11,12] mhz refer to the ac digital block specifications . f 32k1 ilo frequency 15 32 64 khz this specification applies when the ilo has been trimmed. f 32ku ilo untrimmed frequency 5 ? 100 khz after a reset and before the m8c processor starts to execute, the ilo is not trimmed. t xrst external reset pulse width 10 ? ? s dc24m 24 mhz duty cycle 40 50 60 % dc ilo ilo duty cycle 20 50 80 % step24m 24 mhz trim step size ? 50 ? khz fout48m 48 mhz output frequency 46.08 [11] 48 49.92 [11] mhz 4.75 v v dd 5.25 v f max maximum frequency of signal on row input or row output. ? ? 12.96 [11] mhz sr powerup power supply slew rate ? ? 250 v/ms v dd slew rate during power-up. t powerup time between end of por state and cpu code execution ? 16 100 ms power-up from 0 v. t jit_imo [13] 24 mhz imo cycle-to-cycle jitter (rms) ? 200 1200 ps 24 mhz imo long term n cycle-to-cycle jitter (rms) ? 900 6000 ps n = 32 24 mhz imo period jitter (rms) ? 200 900 ps [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 27 of 46 ac gpio specifications ta b l e 1 8 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. figure 5. gpio timing diagram note 14. specification derived from the accuracy of the internal main oscillator (imo) with appropriate trim for v dd range. table 18. ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 12.96 [14] mhz normal strong mode t risef rise time, normal strong mode, cload = 50 pf 3 ? 18 ns v dd = 4.5 to 5.25 v, 10% to 90% t fallf fall time, normal strong mode, cload = 50 pf 2 ? 18 ns v dd = 4.5 to 5.25 v, 10% to 90% t rises rise time, slow strong mode, cload = 50 pf 10 27 ? ns v dd = 3 to 5.25 v, 10% to 90% t falls fall time, slow strong mode, cload = 50 pf 10 22 ? ns v dd = 3 to 5.25 v, 10% to 90% tfallf tfalls trisef trises 90% 10% gpio pin output voltage t falls t fallf t rises t risef [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 28 of 46 ac operational amplifier specifications ta b l e 1 9 and table 20 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. settling times, slew rates, and gain bandwidth are based on the analog continuous time psoc block. power = high and opamp bias = high is not supported at 3.3 v . table 19. 5-v ac operational amplifier specifications symbol description min typ max units t roa rising settling time from 80% of v to 0.1% of v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 3.9 0.72 0.62 s s s t soa falling settling time from 20% of v to 0.1% of v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 5.9 0.92 0.72 s s s sr roa rising slew rate (20% to 80%) (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.15 1.7 6.5 ? ? ? ? ? ? v/s v/s v/s sr foa falling slew rate (20% to 80%) (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.01 0.5 4.0 ? ? ? ? ? ? v/s v/s v/s bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.75 3.1 5.4 ? ? ? ? ? ? mhz mhz mhz e noa noise at 1 khz (power = medium, opamp bias = high) ? 100 ? nv/rt-hz table 20. 3.3-v ac operatio nal amplifier specifications symbol description min typ max units t roa rising settling time from 80% of v to 0.1% of v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high ? ? ? ? 3.92 0.72 s s t soa falling settling time from 20% of v to 0.1% of v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high ? ? ? ? 5.41 0.72 s s sr roa rising slew rate (20% to 80%) (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.31 2.7 ? ? ? ? v/s v/s sr foa falling slew rate (20% to 80%) (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.24 1.8 ? ? ? ? v/s v/s bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high 0.67 2.8 ? ? ? ? mhz mhz e noa noise at 1 khz (power = medium, opamp bias = high) ? 100 ? nv/rt-hz [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 29 of 46 when bypassed by a capacitor on p2[4], the noise of the analog ground signal distributed to each bl ock is reduced by a factor o f up to 5 (14 db). this is at frequencies above the corner frequency defined by the on-chip 8.1 k resistance and the external capacitor. figure 6. typical agnd noise with p2[4] bypass at low frequencies, the opamp noise is proportional to 1/ f, power independent, and determined by device geometry. at high frequencies, increased power level reduces the noise spectrum level. figure 7. typical opamp noise ? 100 1000 10000 0.001 0.01 0.1 1 10 100 fr eq ( khz) nv/rthz 0 0.01 0.1 1.0 10 10 100 1000 10000 0.001 0.01 0.1 1 10 100 freq (khz) nv/rthz ph_ bh ph_ bl pm_ bl pl _ bl [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 30 of 46 ac low power comparator specifications ta b l e 2 1 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v at 25 c and are for design guidance only. ac digital block specifications ta b l e 2 2 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 21. ac low power comparator specifications symbol description min typ max units notes t rlpc lpc response time ? ? 50 s 50 mv overdrive comparator reference set within v reflpc . table 22. ac digital block specifications function description min typ max units notes all functions block input clock frequency v dd 4.75 v ? ? 49.92 [15] mhz v dd < 4.75 v ? ? 25.92 [15] mhz timer input clock frequency no capture, v dd 4.75 v ? ? 49.92 [15] mhz no capture, v dd < 4.75 v ? ? 25.92 [15] mhz with capture ? ? 25.92 [15] mhz capture pulse width 50 [16] ??ns counter input clock frequency no enable input, v dd 4.75 v ? ? 49.92 [15] mhz no enable input, v dd < 4.75 v ? ? 25.92 [15] mhz with enable input ? ? 25.92 [15] mhz enable input pulse width 50 [16] ??ns dead band kill pulse width asynchronous restart mode 20 ? ? ns synchronous restart mode 50 [16] ??ns disable mode 50 [16] ??ns input clock frequency v dd 4.75 v ? ? 49.92 [15] mhz v dd < 4.75 v ? ? 25.92 [15] mhz crcprs (prs mode) input clock frequency v dd 4.75 v ? ? 49.92 [15] mhz v dd < 4.75 v ? ? 25.92 [15] mhz crcprs (crc mode) input clock frequency ? ? 25.92 [15] mhz spim input clock frequency ? ? 8.64 [15] mhz the spi serial clock (sclk) frequency is equal to the input clock frequency divided by 2. spis input clock (sclk) frequency ? ? 4.32 [15] mhz the input clock is the spi sclk in spis mode. width of ss_negated between transmissions 50 [16] ??ns trans- mitter input clock frequency the baud rate is equal to the input clock frequency divided by 8. v dd 4.75 v, 2 stop bits ? ? 49.92 [15] mhz v dd 4.75 v, 1 stop bit ? ? 25.92 [15] mhz v dd < 4.75 v ? ? 25.92 [15] mhz notes 15. accuracy derived from imo with appropriate trim for v dd range. 16. 50 ns minimum input pulse width is based on the input synchronizers running at 24 mhz (42 ns nominal period). [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 31 of 46 ac external clock specifications ta b l e 2 3 list guaranteed maximum and minimum s pecifications for the voltage and temper ature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. ac analog output buffer specifications ta b l e 2 4 and table 25 on page 32 list the guaranteed maximum and minimum specif ications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. receiver input clock frequency the baud rate is equal to the input clock frequency divided by 8. v dd 4.75 v, 2 stop bits ? ? 49.92 [15] mhz v dd 4.75 v, 1 stop bit ? ? 25.92 [15] mhz v dd < 4.75 v ? ? 25.92 [15] mhz table 22. ac digital block specifications (continued) function description min typ max units notes table 23. ac external clock specifications symbol description min typ max units notes f oscext frequency 0 ? 24.24 mhz ? high period 20.5 ? ?ns ? low period 20.5 ? ?ns ? power-up imo to switch 150 ? ? s table 24. 5-v ac analog output buffer specifications symbol description min typ max units notes t rob rising settling time to 0.1%, 1 v step, 100pf load power = low power = high ? ? ? ? 2.5 2.5 s s t sob falling settling time to 0.1%, 1 v step, 100pf load power = low power = high ? ? ? ? 2.2 2.2 s s sr rob rising slew rate (20% to 80%), 1 v step, 100 pf load power = low power = high 0.65 0.65 ? ? ? ? v/ s v/ s sr fob falling slew rate (80% to 20%), 1 v step, 100 pf load power = low power = high 0.65 0.65 ? ? ? ? v/ s v/ s bw obss small signal bandwidth, 20 mv pp , 3 db bw, 100 pf load power = low power = high 0.8 0.8 ? ? ? ? mhz mhz bw obls large signal bandwidth, 1 v pp , 3 db bw, 100 pf load power = low power = high 300 300 ? ? ? ? khz khz [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 32 of 46 ac programming specifications ta b l e 2 6 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 25. 3.3-v ac analog output buffer specifications symbol description min typ max units notes t rob rising settling time to 0.1%, 1 v step, 100 pf load power = low power = high ? ? ? ? 3.8 3.8 s s t sob falling settling time to 0.1%, 1 v step, 100 pf load power = low power = high ? ? ? ? 2.6 2.6 s s sr rob rising slew rate (20% to 80%), 1 v step, 100 pf load power = low power = high 0.5 0.5 ? ? ? ? v/ s v/ s sr fob falling slew rate (80% to 20%), 1 v step, 100 pf load power = low power = high 0.5 0.5 ? ? ? ? v/ s v/ s bw obss small signal bandwidth, 20 mv pp , 3 db bw, 100 pf load power = low power = high 0.7 0.7 ? ? ? ? mhz mhz bw obls large signal bandwidth, 1 v pp , 3 db bw, 100 pf load power = low power = high 200 200 ? ? ? ? khz khz table 26. ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data setup time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? 10 40 [17] ms t write flash block write time ? 40 160 [17] ms t dsclk data out delay from falling edge of sclk ? ? 45 ns v dd > 3.6 v t dsclk3 data out delay from falling edge of sclk ? ? 50 ns 3.0 v v dd 3.6 v t prgh total flash block program time (t eraseb + t write ), hot ? ? 100 [17] ms t j 0 c t prgc total flash block program time (t eraseb + t write ), cold ? ? 200 [17] ms t j < 0 c note 17. for the full temperature range, the user must employ a temper ature sensor user module (flashtemp) or other temperature senso r, and feed the result to the temperature argument before writing. refer to the flash apis application note an2015 for more information. [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 33 of 46 ac i 2 c specifications ta b l e 2 7 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. figure 8. definition for timing for fast/standard mode on the i 2 c bus table 27. ac characteristics of the i 2 c sda and scl pins for v dd symbol description standard mode fast mode units notes min max min max f scli2c scl clock frequency 0 100 [18] 0 400 [18] khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? s t highi2c high period of the scl clock 4.0 ?0.6 ? s t sustai2c setup time for a repeated start condition 4.7 ?0.6 ? s t hddati2c data hold time 0 ?0 ? s t sudati2c data setup time 250 ? 100 [19] ?ns t sustoi2c setup time for stop condition 4.0 ?0.6 ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? s t spi2c pulse width of spikes are suppressed by the input filter. ? ? 0 50 ns i2c_sda i2c_scl s sr s p t bufi2c t spi2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c start condition repeated start condition stop condition notes 18. f scli2c is derived from sysclk of the psoc. this specification assumes that sysclk is operating at 24 mhz, nominal. if sysclk is at a lower frequency, then the f scli2c specification adju sts accordingly. 19. a fast-mode i2c-bus device can be used in a standard-mode i2c-bus system, but the requirement t sudati2c 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl si gnal. if such device does stretch the low period of the scl sig nal, it must output the next data bit to the sda line t rmax + t sudati2c = 1000 + 250 = 1250 ns (according to the standard-mode i2 c-bus specification) before the scl line is released. [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 34 of 46 packaging information this section illustrates the package specif ication for the cy8c24x94 psoc devices, alo ng with the thermal impedance for the pac kage and solder reflow peak temperatures. note emulation tools may require a larger area on the target pcb t han the chip's footprint. for a detailed description of the emula tion tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com . figure 9. 56-pin (8 8 mm) qfn (punched) important note for information on the preferred di mensions for mounting qfn packages, see the following application note, application notes for surface mount assembly of amkor's microleadframe (mlf) packages available at http://www.amkor.com . pinned vias for thermal conduction are not required for the low power psoc device. thermal impedances solder reflow specifications ta b l e 2 9 shows the solder reflow temperature limits that must not be exceeded. solderable exposed pad 001-12921 *b table 28. thermal impedance per package package typical ja [20] typical jc 56-pin qfn [21] 19 c/w 1.7 c/w table 29. solder reflow specifications package maximum peak temperature (t c ) maximum time above t c ? 5 c 56-pin qfn 260 c 30 seconds notes 20. t j = t a + power ja. 21. to achieve the thermal impedance specified for the qfn package , refer to the application notes for surface mount assembly of amkor's microleadframe (mlf) packages available at http://www.amkor.com . [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 35 of 46 tape and reel information figure 10. 56-pin (8 8 mm) qfn (punched) carrier tape drawing table 30. tape and reel specifications package cover tape width (mm) hub size (inches) minimum leading empty pockets minimum trailing empty pockets standard full reel quantity 56-pin qfn 13.1 7 42 25 2000 51-51165 *b [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 36 of 46 development tool selection software psoc designer at the core of the psoc development software suite is psoc designer, used to generate psoc firmware applications. psoc designer is available free of charge at http://www.cypress.com and includes a free c compiler. psoc programmer flexible enough to be used on the bench in development, yet suitable for factory programming, psoc programmer works either as a standalone programming application or it can operate directly from psoc designer or psoc express. psoc programmer software is compatible with both psoc ice-cube in-circuit emulator and psoc miniprog. psoc programmer is available free of charge at http://www.cypress.com . development kits all development kits c an be purchased from the cypress online store . the online store also has the most up to date information on kit contents, descriptions, and availability. cy3215-dk basic development kit the cy3215-dk is for prototyping and development with psoc designer. this kit supports in-circuit emulation and the software interface allows users to run, halt, and single step the processor and view the contents of specif ic memory locations. advanced emulation features are also su pported through psoc designer. the kit includes: ice-cube unit 28-pin pdip emulation pod for cy8c29466-24pxi 28-pin cy8c29466-24pxi pdip psoc device samples (two) psoc designer software cd issp cable minieval socket programming and evaluation board backward compatibility cable (for connecting to legacy pods) universal 110/220 power supply (12 v) european plug adapter usb 2.0 cable getting started guide development kit registration form cy3280-24x94 universal capsense controller board the cy3280-24x94 controller board is an additional controller board for the cy3280-bk1 universal capsense controller kit. the universal capsense controller kit is designed for easy prototyping and debug of capsense designs with pre-defined control circuitry and plug-in hardware. the cy3280-24x94 kit contains no plug-in hardware. ther efore, it is only usable if plug-in hardware is purchased as part of the cy3280-bk1 kit or other separate kits. the kit includes: cy3280-24x94 universal capsense controller board cy3240-i2usb bridge board cy3210 psoc miniprog1 programmer cy3280-24x94 quick start usb retractable cable (a to mini-b) psoc express installation cd psoc designer and psoc programmer cd cy3280-24x94 universal capsense controller kit cd evaluation tools all evaluation tools can be purchased from the cypress online store . the online store also has the most up to date information on kit contents, descripti ons, and availability. cy3210-psoceval1 the cy3210-psoceval1 kit features an evaluation board and the miniprog1 programming unit. the evaluation board includes an lcd module, potentiometer, leds, and plenty of bread- boarding space to meet all of your evaluation needs. the kit includes: evaluation board with lcd module miniprog programming unit 28-pin cy8c29466-24pxi pdip psoc device sample (2) psoc designer software cd getting started guide usb 2.0 cable cy3210-24x94 evaluation pod (evalpod) psoc evalpods are pods that c onnect to the ice in-circuit emulator (cy3215-dk kit) to allow debugging capability. they can also function as a standalone device without debugging capability. the evalpod has a 28-pin dip footprint on the bottom for easy connection to development kits or other hardware. the top of the evalpod has prototyp ing headers for easy connection to the device's pins. cy3210-24x94 provides evaluation of the cy8c24x94 psoc device family. [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 37 of 46 device programmers all device programmers can be purchased from the cypress online store. cy3210-miniprog1 the cy3210-miniprog1 kit allows a user to program psoc devices via the miniprog1 programming unit. the miniprog is a small, compact prototyping programmer that connects to the pc via a provided usb 2.0 cable. the kit includes: miniprog programming unit minieval socket programming and evaluation board 28-pin cy8c29466-24pxi pdip psoc device sample 28-pin cy8c27443-24pxi pdip psoc device sample psoc designer software cd getting started guide usb 2.0 cable cy3207issp in-system serial programmer (issp) the cy3207issp is a production programmer. it includes protection circuitry and an industria l case that is more robust than the miniprog in a production-programming environment. note : cy3207issp needs special software and is not compatible with psoc programmer. the kit includes: cy3207 programmer unit psoc issp software cd 110 ~ 240 v power supply, euro-plug adapter usb 2.0 cable accessories (emula tion and programming) table 31. emulation and programming accessories part # pin package flex-pod kit [22] foot kit [23] adapter [24] CY8C24894-24LFXA 56-pin qfn cy3250-24x94qfn cy3250-56qfn-fk as-56-28-01ml-6 notes 22. flex-pod kit includes a practice flex-pod and a practice pcb, in addition to two flex-pods. 23. foot kit includes surface mount feet that are soldered to the target pcb. 24. programming adapter converts non-dip package to dip footprin t. specific details and ordering information for each of the ada pters are found at http://www.emulation.com. [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 38 of 46 ordering information ordering code definitions table 32. cy8c24x94 psoc device?s key features and ordering information package ordering code flash (bytes) sram (bytes) temperature range digital blocks analog blocks digital i/o pins analog inputs analog outputs xres pin 56-pin (8 8 mm) qfn, punched CY8C24894-24LFXA 16 k 1 k ?40 c to +85 c 4 6 49 47 2 yes 56-pin (8 8 mm) qfn, punched (tape and reel) CY8C24894-24LFXAt 16 k 1 k ?40 c to +85 c 4 6 49 47 2 yes cy 8 c 24 xxx-spxx package type: thermal rating: px = pdip pb-free a = automotive ?40 c to +85 c sx = soic pb-free c = commercial pvx = ssop pb-free e = automotive extended ?40 c to +125 c lfx/lkx = qfn pb-free i = industrial ax = tqfp pb-free bvx = vfbga pb-free cpu speed: 24 mhz part number family code technology code: c = cmos marketing code: 8 = psoc company id: cy = cypress [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 39 of 46 reference information acronyms ta b l e 3 3 lists the acronyms that are used in this document. reference documents cy8cplc20, cy8cled16p01, cy8c29x66, cy8c27x43, cy8c24 x94, cy8c24x23, cy8c24x23a, cy8c22x13, cy8c21x34, cy8c21x23, cy7c64215, cy7c603xx, cy8cnp1xx, and cywusb6953 psoc ? programmable system-on-chip technical reference manual (trm) (001-14463) design aids ? reading and writing psoc ? flash ? an2015 (001-40459) understanding datasheet jitter specifications for cypress timing products ? an5054 (001-14503) application notes for surface mount assembly of amkor's microleadframe (mlf) packages ? available at http://www.amkor.com . table 33. acronyms used in this datasheet acronym description acronym description ac alternating current mips million instructions per second adc analog-to-digital converter pcb printed circuit board aec automotive electronics council pdip plastic dual in-line package api application programming interface pll phase-locked loop cpu central processing unit por power-on reset crc cyclic redundancy check ppor precision por ct continuous time psoc ? programmable system-on-chip dac digital-to-analog converter pwm pulse-width modulator dc direct current or duty cycle qfn quad flat no leads dtmf dual-tone multi-frequency rms root mean square eeprom electrically erasabl e programmable read-only memory sar successive approximation register extclk external clock sc switched capacitor gpio general purpose i/o scl / sclk serial clock i 2 c inter-integrated circuit sda serial data ice in-circuit emulator slimo slow imo ide integrated development env ironment smp switch mode pump ilo internal low-speed oscillator so ic small-outline integrated circuit imo internal main oscillator spi serial peripheral interface i/o input/output sram sta tic random-access memory irda infrared data association srom supervisory read-only memory issp in-system serial programming tqfp thin quad flat pack lcd liquid crystal display uart universal asynchronous receiver transmitter led light-emitting diode usb universal serial bus lpc low power comparator wdt watchdog timer lvd low voltage detect xres external reset mcu microcontroller unit [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 40 of 46 document conventions units of measure the following table lists the units of me asure that are used in this document. numeric conventions hexadecimal numbers are represented with all letters in uppercase wi th an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? pref ix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, ?01010100b? or ?0 1000011b?). numbers not indicated by an ?h ?, ?b?, or ?0x? are in decimal format. table 34. units of measure symbol unit of measure symbol unit of measure c degree celsius mv pp millivolts peak-to-peak db decibel na nanoampere ff femtofarad ns nanosecond kb 1024 bytes nv nanovolt khz kilohertz ohm k kilohm % percent mhz megahertz pa picoampere a microampere pf picofarad s microsecond ps picosecond v microvolt rt-hz root hertz ma milliampere v volt ms millisecond w watt mv millivolt glossary active high 1. a logic signal having its asserted state as the logic 1 state. 2. a logic signal having the logic 1 state as the higher voltage of the two states. analog blocks the basic programmable opam p circuits. these are sc (switched capa citor) and ct (continuous time) blocks. these blocks can be interconn ected to provide adcs, dacs , multi-pole filt ers, gain stages, and much more. analog-to-digital converter (adc) a device that changes an analog signal to a digital signal of corresponding magnitude. typically, an adc converts a voltage to a digital number. the digital-to-analog converter (dac) performs the reverse operation. application programming interface (api) a series of software routines that comprise an interfac e between a computer applicat ion and lower level services and functions (for example, user modules and libraries). apis serve as building blocks for prog rammers that create software applications. asynchronous a signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. bandgap reference a stable voltage reference design that matches the posit ive temperature coefficient of vt with the negative temperature coefficient of vbe, to produce a zero temperature coefficient (ideally) reference. bandwidth 1. the frequency range of a message or information processing system measured in hertz. 2. the width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specific ally as, for example, full width at half maximum. [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 41 of 46 bias 1. a systematic deviation of a value from a reference value. 2. the amount by which the average of a set of values departs from a reference value. 3. the electrical, mechanical, magnetic, or other force (field ) applied to a device to establish a reference level to operate the device. block 1. a functional unit that performs a single function, such as an oscillator. 2. a functional unit that may be configured to perform one of several functions, such as a digital psoc block or an analog psoc block. buffer 1. a storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. usually refers to an area reserved for i/o operations, into which da ta is read, or from which data is written. 2. a portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. an amplifier used to lower the output impedance of a system. bus 1. a named connection of nets. bundling nets together in a bus makes it easier to r oute nets with similar routing patterns. 2. a set of signals performing a common function and carry ing similar data. typically represented using vector notation; for example, address[7:0]. 3. one or more conductors that serve as a co mmon connection for a group of related devices. clock the device that generates a period ic signal with a fixed frequency and duty cycle. a clock is sometimes used to synchronize different logic blocks. comparator an electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. compiler a program that translates a high leve l language, such as c, into machine language. configuration space in psoc devices, the register space accessed when the xio bit, in the cpu_f register, is set to ?1?. crystal oscillator an oscillator in whic h the frequency is controlled by a piezoelectric crystal. typically a piezoelectric crystal is less sensitive to ambient te mperature than other circuit components. cyclic redundancy check (crc) a calculation used to detect errors in data communic ations, typically performed using a linear feedback shift register. similar calculations may be used for a va riety of other purposes such as data compression. data bus a bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. more generally, a set of signals used to convey data between digital functions. debugger a hardware and software system that allows you to analyze the operation of the system under development. a debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory. dead band a period of time when neither of two or more signals are in their active state or in transition. digital blocks the 8-bit logic bl ocks that can act as a counter, timer, serial receiver, serial transm itter, crc generator, pseudo-random number generator, or spi. digital-to-analog converter (dac) a device that changes a digital signal to an analog signal of corresponding magnitude. the analog-to-digital converter (adc) performs the reverse operation. glossary (continued) [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 42 of 46 duty cycle the relations hip of a clock period high time to its low time, expressed as a percent. emulator duplicates (provides an emulation of) the functions of one system with a different system, so that the second system appears to behave like the first system. external reset (xres) an active high signal that is driven into the psoc devi ce. it causes all operation of the cpu and blocks to stop and return to a pre-defined state. flash an electrically programmable an d erasable, non-volatile technology that provides you the programmability and data storage of eproms, plus in-system erasability. non-volatile means that the data is retained when power is off. flash block the smallest amount of flash rom space that may be programmed at one time and the smallest amount of flash space that may be protected. frequency the number of cycles or events pe r unit of time, for a periodic function. gain the ratio of output current, voltage, or power to input current, voltage, or power, respectively. gain is usually expressed in db. i 2 c a two-wire serial computer bus by philips semiconducto rs (now nxp semiconductors). it is used to connect low-speed peripherals in an embedded system. the original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building contro l electronics. i2c uses only two bi-directional pins, clock and data, both running at the v dd suppy voltage and pulled high with resistors. the bus operates up to100 kbits/second in stan dard mode and 400 kbits/second in fast mode. ice the in-circuit emulator that allows you to test the project in a hardware environm ent, while viewing the debugging device activity in a software environment (psoc designer). input/output (i/o) a device that introduces da ta into or extracts data from a system. interrupt a suspension of a process, such as the execution of a computer progra m, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service routine (isr) a block of code that normal code exec ution is diverted to when the cpu receives a hardware interrupt. many interrupt sources may each exist with its own priority and individual isr code block. each isr code block ends with the reti instruction, returning t he device to the point in the program w here it left normal program execution. jitter 1. a misplacement of the timing of a transition from its ideal position. a ty pical form of corruption that occurs on serial data streams. 2. the abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequen cy or phase of successive cycles. low voltage detect (lvd) a circuit that senses v dd and provides an interrupt to the system when v dd falls below a sele cted threshold. m8c an 8-bit harvard-architecture microprocessor. the mi croprocessor coordinates all activity inside a psoc by interfacing to the flash, sram, and register space. master device a device that controls the timing for data exch anges between two devices. or when devices are cascaded in width, the master device is the one that controls th e timing for data exchanges between the cascaded devices and an external interface. the controlled device is called the slave device . glossary (continued) [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 43 of 46 microcontroller an integrated circuit chip that is designed pr imarily for control systems and products. in addition to a cpu, a microcontroller typically incl udes memory, timing circuits, and i/o circuitry. the reason for this is to permit the realization of a controller with a minima l quantity of chips, thus achieving ma ximal possible miniaturization. this in turn, reduces the volume and the cost of the cont roller. the microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal the reference to a circuit containing both analog and digital techniques and components. modulator a device that imposes a signal on a carrier. noise 1. a disturbance that affects a signal and that may distort the information carried by the signal. 2. the random variations of one or mo re characteristics of any entity such as voltage, current, or data. oscillator a circuit that may be crystal controlled and is used to generate a clock frequency. parity a technique for testing transmitted data. typically, a bi nary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). phase-locked loop (pll) an electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. pinouts the pin number assignment: the relation between the logical inputs and outputs of the psoc device and their physical counterparts in the printed circuit board (pcb) package. pinouts involve pin numbers as a link between schematic and pcb design (both being computer generated files) and may also involve pin names. port a group of pins, usually eight. power-on reset (por) a circuit that forces the psoc device to reset when the volta ge is below a pre-set level. th is is one type of hardware reset. psoc ? cypress semiconductor?s psoc ? is a registered trademark and progra mmable system-on-chip? is a trademark of cypress. psoc designer? the software for cypress? programmable system-on-chip technology. pulse width modulator (pwm) an output in the form of duty cycle which varies as a function of the applied value. ram an acronym for random access memory. a data-storage device from which data can be read out and new data can be written in. register a storage device with a specific capacity, such as a bit or byte. reset a means of bringing a system back to a know n state. see hardware reset and software reset. rom an acronym for read only memory. a data-storage devi ce from which data can be read out, but new data cannot be written in. serial 1. pertaining to a process in which all events occur one after the other. 2. pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. settling time the time it takes for an output signal or value to stabilize after the input has changed from one value to anothe r. glossary (continued) [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 44 of 46 shift register a memory storage dev ice that sequentially shifts a wo rd either left or right to ou tput a stream of serial data. slave device a device that allows another device to control the timing for data exchanges between two devices. or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external inte rface. the controlling device is called the master device. sram an acronym for static random access memory. a memory device where you can store and retrieve data at a high rate of speed. the term static is used because, after a value is loaded into an sram cell, it remains unchanged until it is explicitly altered or unt il power is removed from the device. srom an acronym for supervisory read only memory. the srom holds code that is used to boot the device, calibrate circuitry, and perform flash operations. the functions of the srom may be accessed in normal user code, operating from flash. stop bit a signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1. a signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. a system whose operation is syn chronized by a clock signal. tri-state a function whose output can adopt three states: 0, 1, and z (hig h-impedance). the function does not drive any value in the z state and, in many respects, may be c onsidered to be disconnected from the rest of the circuit, allowing another output to drive the same net. uart a uart or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits. user modules pre-built, pre-tested hardware/f irmware peripheral functions that take ca re of managing and configuring the lower level analog and digi tal psoc blocks. user module s also provide high level api (application programming interface) for the peripheral function. user space the bank 0 space of the register map. the registers in this bank are more likely to be modified during normal program execution and not just during initialization. register s in bank 1 are most likely to be modified only during the initialization phase of the program. v dd a name for a power net meaning "voltage drain." the most positive power supply signal. usually 5 v or 3.3 v. v ss a name for a power net meaning "voltage source." the most negative power supply signal. watchdog timer a timer that must be serviced periodically. if it is not serviced, the cpu resets after a specified period of tim e. glossary (continued) [+] feedback
cy8c24894 document number: 001-53754 rev. *d page 45 of 46 document history page document title: cy8c24894 automotive psoc ? programmable system-on-chip? document number: 001-53754 revision ecn orig. of change submission date description of change ** 2715097 masj 06/08/09 new datasheet. *a 2782580 btk 10/09/09 updated features section. updated text of psoc functional overview section. updated getting started sect ion. made corrections and minor text edits to pinouts section. changed the name of so me sections to improve consistency. improved formatting of the register tabl es. added clarifying comments to some electrical specifications. fixed all ac spec ifications to conform to a 4% or 8% imo accuracy. made other miscellaneou s minor text edits. deleted some non-applicable or redundant information. improved and edited content in devel- opment tool selection section. impr oved the bookmark structure. changed flash ent , v cmoa , the dc por and lvd specific ations, and the dc analog reference specifications according to masj directives. added t xrst , dc24m, and 3.3 v dc operational am plifier specifications. *b 2822792 btk/aesa 12/07/09 added t prgh, t prgc, i ol , i oh , f 32ku , dc ilo , and t powerup electrical speci- fications. updated the footnotes of table 16, ?dc programming specifications,? on page 25. added maximum values and updated typical values for t eraseb and t write electrical specifications. replaced t ramp electrical specification with sr powerup electrical specification. added ?contents? on page 2. *c 2888007 njf 03/30/10 updated cypress website links. removed reference to psoc designer 4.4 in psoc designer software subsystems updated the analog system . added t baketemp and t baketime parameters in absolute maximum ratings . updated ac chip-level specifications . updated packaging information . removed third party tools and build a psoc emulator into your board. updated links in sales, solutions, and legal information . *d 3272922 btk/njf 06/02/11 updated figure 8 on page 33 to improve clarity. updated wording, formatting, and notes of the ac digital block specifications table to improve clarity. added v ddp, v ddlv , and v ddhv electrical specifications to give more infor- mation for programming the device. updated solder reflow specifications to give more clarity. updated the jitter specifications. updated psoc device characteristics table. updated the f 32ku electrical specification. updated note for r pd electrical specification. updated note for the t stg electrical specification to add more clarity. added tape and reel specifications section. added c l electrical specification. updated dc analog reference specifications . changed ?nc? pins on the device to ?dnc? pins. corrected information about the exposed pad to clarify that it is not internally connected. [+] feedback
document number: 001-53754 rev. *d revised june 2, 2011 page 46 of 46 all products and company names mentioned in this document may be the trademarks of their respective holders. cy8c24894 ? cypress semiconductor corporation, 2009-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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